The present invention relates to placement of clock distribution networks and fabrication of conductive lines in semiconductor integrated circuit structures.
FIG. 1 shows a tree-like clock distribution network 110 designed to distribute a clock signal with a minimum clock skew in an integrated circuit. The clock signal is received at a terminal 120 and distributed to terminals 130 at the leaves of tree 110. Terminals 130 are connected to inputs of circuit blocks 140 such as registers, flip flops, latches, logic gates, etc. The network tree is provided by conductive lines 150. The wires 150 that connect the tree nodes of each given tree level to the tree nodes of any given adjacent level have the same dimensions. Buffers (amplifiers) 160 are located at selected points in the tree to amplify the clock signal. In order to minimize the clock skew, each clock path from terminal 120 to a terminal 130 has the same dimensions, and the respective buffers 160 in each path are identical to each other. These rules are sometimes violated to compensate for different loading at different terminals 130. For example, the lengths or widths of individual wires 150 can be adjusted.
FIG. 2 is a plan view of a grid type clock distribution network. Lines 150 form a grid, with the horizontal and vertical lines being connected together at the points of intersection. The clock signal is delivered to terminal 120 at the grid center, amplified by buffer 160.1, and distributed to buffers 160.2 at the grid edges. Each buffer 160.2 drives a horizontal or vertical line 150. Clock terminals 130 are positioned on lines 150 and connected to circuit blocks such as blocks 140 of FIG. 1.
Other clock distribution networks are also known. For example, the tree and grid networks can be combined. A circuit block 140 of FIG. 1 can be replaced with a grid network or a local clock generation circuit. See U.S. Pat. No. 6,311,313 entitled xe2x80x9cX-Y GRID TREE CLOCK DISTRIBUTION NETWORK WITH TUNABLE TREE AND GRID NETWORKSxe2x80x9d issued Oct. 30, 2001 to Camporese et al., incorporated herein by reference.
A perfect placement of a clock distribution network on a semiconductor die can be difficult due to the presence of other circuitry. A modern integrated circuit may include up to eight metal layers. The clock distribution network uses one of these layers for lines 150. Another metal layer, underlying the lines 150, is used for a ground plane or a ground grid to shield the underlying circuitry from the electromagnetic field generated by high frequency clock signals on lines 150. These two layers are separated by a dielectric. The speed of signal propagation along the clock distribution network is affected by the capacitance between the lines 150 and the ground plane or grid. The capacitance is not uniform across the integrated circuit due to local variations of the dielectric thickness and the capacitive coupling between the lines 150 and other nearby switching lines. As a result, it is difficult to control the impedance of lines 150 and therefore the clock propagation speed.
Further, the ground plane or grid consumes valuable area, increases the cost and complexity of the integrated circuit, and sometimes does not completely eliminate the electromagnetic interference problem because the position of the ground plane or grid can be restricted to allow the same metal layer to be used for other circuit elements.
In FIG. 3, the clock distribution network is removed from die 310 containing the clocked circuitry, and placed on a separate (xe2x80x9csecondaryxe2x80x9d) die 320. The dies 310 and 320 are bonded together in a flip chip manner with solder balls 321. The two dies are offset from each other so that each die has contact pads not covered by the other die. These contact pads are shown as pads 322 on die 310 and pads 323 on die 320. Pads 322, 323 are connected to external circuitry (not shown) with solder balls 313. Alternatively, die 320 can be made larger than die 310 to make room for contact pads 323. See U.S. Pat. No. 6,040,203 entitled xe2x80x9cCLOCK SKEW MINIMIZATION AND METHOD FOR INTEGRATED CIRCUITSxe2x80x9d, issued Mar. 21, 2000 to Bozso et al., incorporated herein by reference.
The invention is defined by the appended claims which are incorporated into this section by reference. Some features of the invention are summarized immediately below.
The inventor has observed that in the structure of FIG. 3 significant electromagnetic interference, as well as parasitic capacitance, can be associated with the transfer of signals and power and ground voltages between contact pads 322, 323 and circuit blocks in dies 310 and 320. The signal, power, and ground paths between contact pads 322 and blocks 140 go through conductive lines 324. The signal, power and ground paths between contact pads 323 and circuit 310, and the paths between contact pads 323 and circuitry 325 in die 320, go through conductive lines 326. Depending on the layout, the lines 324, 326 can be parallel to lines 150, or make small angles with lines 150. The small angles when combined with small spacing between a line 324 or 326 and a line 150 may lead to significant electromagnetic interference and parasitic capacitance.
In some embodiments of the invention, some or all of the contact pads 323, and at least a contact pad that serves as the input terminal of the clock distribution network, are moved to the bottom of die 320. The bottom contact pads 323 are connected to circuitry at the top of the die by means of conductive features forming large angles (e.g. 90xc2x0) with the top and bottom surfaces of die 310. Since large portions of lines 150 extend along the top surface of die 310, the electromagnetic interference and the parasitic capacitance can be reduced.
In some embodiments, contact pads 322 are omitted. The conductive paths to and from die 310 are through die 320. Further reduction of the electromagnetic interference and the parasitic capacitance can be achieved as a result. Also, the structure occupies less area.
The bottom contact pads on die 320 can be bonded to contact pads on another integrated circuit or a wiring substrate. In this case, the die 320 serves as a semiconductor xe2x80x9cinterposerxe2x80x9d positioned between die 310 and other integrated circuits or between die 310 and a wiring substrate.
Die 320 may include ground planes or grids or other grounded lines to shield the circuitry above and below the interposer from the clock distribution network.
In another embodiment, several interposers are provided, with different parts of a clock distribution network on different interposers.
In some embodiments, the clock distribution lines 150 (FIGS. 1, 2) are formed in trenches etched in a semiconductor substrate. The RC value of lines 150 can be lowered by making the trenches deeper, without increasing the lateral area occupied by the RC lines. Also, the RC value, and hence the clock skew, become more controllable.
Other conductive lines, not belonging to the clock distribution network, can be formed in such trenches.
Other embodiments and variations are described below. The invention is defined by the appended claims.